1. Field of the Invention
The present invention relates to a phase interpolator, particularly, that of a Clock Data Recovery (CDR) system.
2. Description of the Related Arts
Phase interpolators are widely used to adjust phase differences among system clocks in Clock Data Recovery (CDR) systems and phase detection systems, in which accurate interleaving clocks are required for the front-end samplers to latch the input data.
Conventional phase interpolators (PI) use analog elements (adder, multiplier or mixer, amplifier, etc.) to adjust a phase difference between two reference clock(s). Since time delays exist in those analog elements, delay compensation elements are necessary to adjust phase among reference clocks and interpolated clock. Moreover, there are different kinds of time jitter and variation in delay compensation elements. The time delays of such elements are also sensitive to change in incoming data rate, process parameters and temperature.
FIG. 1 shows an example of a conventional clock data recovery system.
In the example of a clock data recovery (CDR) system shown in FIG. 1, there are parallel front-end samplers 10-1, 10-2, 10-3, . . . , 10-n, a demultiplexer (DEMUX) 11, a phase detect unit 12, 2 non-linearity correction coders 13-1 and 13-2, delay compensation elements (t_dly) 14-1 and 14-2, a phase interpolator 15 and a charge pump 16. Input data Din is serial data and the input data Din is latched by samplers 10-1, 10-2, 10-3, . . . , 10-n in parallel. The samplers 10-1, 10-2, 10-3, . . . , 10-n are latches or flip-flops for example. Each sampler 10-1, 10-2, 10-3, . . . , 10-n latches data at different timing, which means the input data Din is transformed from serial data to parallel data. When n samplers are provided the input data Din is converted to n parallel data. The parallelized input data Q's are input to the demultiplexer 11 where the parallelized input data are synchronized with each other and output as output data Dout which is parallel data. The demultiplexer 11 detects phase information of the parallelized input data Q's and outputs it to the phase detect unit 12. The phase detect unit 12 outputs signals which represent differences in phases between the parallelized input data Q's. The output signals from the phase detect unit 12 are fed to the charge pump 16 and the non-linearity correction coder 13-1 and 13-2. The charge pump 16 converts the output of the phase detect unit 12 to a control voltage for a VCO (voltage controlled oscillator) which generates reference clock signals (CK1 and CK2) for operation of the data recovery system. By changing the control voltage the phases or frequencies of the reference clock signals (CK1 and CK2) can be changed. The outputs of the phase detect unit 12 which are input to the non-linearity correction coder 13-1 and 13-2 are converted to delay amount control voltages for delay compensation elements 14-1 and 14-2 and weight coefficients (g1 and g2) for the phase interpolator 15. The non-linearity correction coder 13-1 and 13-2 are composed of lookup tables, for example, which convert outputs of the phase detect unit 12 to suitable voltage signals for delay compensation elements 14-1 and 14-2 and weight coefficients g1 and g2 for the phase interpolator 15. The reference clock signals CK1 and CK2 are delayed by the delay compensation elements 14-1 and 14-2 to be clock signals ACK1 and ACK2 for samplers 10-1 and 10-3, respectively, for example. The phase interpolator 15 receives the reference clocks CK1 and CK2 and weight coefficients g1 and g2 in order to make an interpolated clock signal ICK depending on values of weight coefficients g1 and g2. The interpolated clock signal ICK is used to latch data of intermediate timing between those of ACK1 and ACK2. If the number of Q's is three only one phase interpolator is provided but if the number of Q's is more than three a plurality of phase interpolators are provided.
FIG. 2 is a timing chart of the conventional data recovery system shown in FIG. 1.
There are phase errors between ICK and reference clocks (CK1, CK2) in conventional phase interpolators. If phase error occurs erroneous data will exist in the output of the data recovery system.
In FIG. 2, the input data Din is shown as signals with data period T. The signal ACK1 is used to latch data at timing (1) for each n data period. Also the signal ACK2 is used to latch data at timing (2) for each n data period. And the signal ICK is used to latch data at timing (3) for each n data period. Here only three signals for latching are shown. However, in order to latch n data at different timing (n−3) more signals for latching are needed. We focus on only three signals ACK1, ACK2 and ICK, which is enough to understand the problems of the conventional phase interpolator.
As indicated as “unstable phases” in FIG. 2, the phase shift of ACK1, ACK2 and ICK occurs in the conventional phase interpolator. This phase shift causes erroneous data occurrence in parallelized input data Q's. Therefore, synchronized data Dout which is generated from the parallelized input data Q's includes erroneous data. In FIG. 2 only one figure is shown for Dout because as Dout has synchronized n data sequences it is space saving to represent n bits in one data period. Therefore, the data period (4) of Dout represents n parallel bit data and the data period (5) represents n parallel bit data with erroneous data.
FIGS. 3A and 3B show a conventional phase interpolator used in the conventional clock data recovery system shown in FIG. 1.
As shown in FIG. 3A, the conventional phase interpolator comprises multipliers 20-1 and 20-2, an analog adder 21 and an amplifier 22. The signal CK1 is multiplied by g1 by multiplier 20-1 and the signal CK2 is multiplied by g2 by multiplier 20-2. The outputs from multiplier 20-1 and 20-2 are input to the analog adder 21 and the outputs are added. As explained below the intermediate phase signal is generated by adding the outputs of multiplier 20-1 and 20-2. The amplifier 22 amplifies the output of the analog adder 21 in order to make the amplitude of the intermediate signal suitable for the signal ICK.
Because analog. elements (analog adder 21, multiplier 20-1 and 20-2, amplifier 22) are used, delay in a phase of ICK occurs due to inherent operation delay of these analog elements. In order to adjust phases of two reference clocks CK1 and CK2 with respect to the phase of ICK so that proper latch operation can be performed, the signals ACK1 and ACK2 are generated from the signals CK1 and CK2 by delaying these signals.
Since time delays exist in those analog elements, delay compensation elements 14-1 and 14-2 are necessary to adjust phase among reference clocks CK1 and CK2 and interpolated clock ICK. The delay time occurred in a conventional phase interpolator is denoted by “t_dly”. To compensate for the delay time (t_dly), both CK1 and CK2 are delayed to generate ACK1 and ACK2.
Mathematically, t_dly≅time delay between CK1 and ICK≅time delay between CK2 and ICK
In FIG. 3B, the reference clocks CK1 and CK2 are shown as signals with period Tc. The signals CK1 and CK2 are phase-shifted with respect to each other. The interpolated signal shown as a desired output by the dotted line is required. But the output of the analog adder AD and the output of the amplifier ICK (real output) are delayed from the desired output by t_dly. In order to match the phases between CK1, CK2 and ICK the phases of CK1 and CK2 should be delayed. Therefore, the signals ACK1 and ACK2 respectively delayed from CK1 and CK2 by t_dly are generated.
However, phase mismatch occurs because t_dly varies with values of g1, g2, and operating conditions.
Worse, since the phase difference between CK1 and ICK is a non-linear function of {g1,g2}, the non-linearity correction coders are necessary in the conventional clock data recovery system.
Addition of these non-linearity decoders increases the complexity and circuit scale of the clock data recovery system. Due to the large scale of the circuit and time delays in each circuit block, the phase error cannot be compensated immediately. As a result, there will be erroneous data in the recovered data. This will result in errors in the demultiplexed data.
The following is a description of the relation of {g1,g2} and the phase difference between CK1 and ICK.
In a conventional phase interpolator, ICK can be considered as a shaped waveform of (g1·CK1+g2·CK2). The weights g1 and g2 adjust the proportion of likeness to {CK1, CK2}. When g1 is larger than g2, the interpolated ICK is more similar to CK1 than to CK2, and when g2 is larger than g1, the interpolated ICK is more similar to CK2 than CK1. If both of CK1 and CK2 are sinusoidal waves, refer to the equation (1) and equation (2) below. If CK1 and CK2 are triangular waves or square waves, the interpolated clock is a summation of all the sinusoidal harmonics of the g1·CK1 and g2·CK2.
Below is an explanation in the case of a sinusoidal wave being used to describe a waveforms phase in a conventional phase interpolator. Details of calculation are described as follows.
If both of CK1 and CK2 are sinusoidal waves, they can be expressed as CK1=sin(wt) and CK2=sin(wt−k), where w is the angular frequency of clocks (CK1 and CK2), t is time, and k is the phase difference between CK1 and CK2.
As a result, the waveform expression of AD in FIG. 3B is given by
                                                                        AD                ⁡                                  (                  t                  )                                            =                                                g                  ⁢                                                                          ⁢                                      1                    ·                                          sin                      ⁡                                              (                        wt                        )                                                                                            +                                  g                  ⁢                                                                          ⁢                                      2                    ·                                          sin                      ⁡                                              (                                                  wt                          -                          k                                                )                                                                                                                                                                    =                                                g                  ⁢                                                                          ⁢                                      1                    ·                                          sin                      ⁡                                              (                        wt                        )                                                                                            +                                  g                  ⁢                                                                          ⁢                                      2                    ·                                          [                                                                                                    sin                            ⁡                                                          (                              wt                              )                                                                                ⁢                                                      cos                            ⁡                                                          (                              k                              )                                                                                                      -                                                                              sin                            ⁡                                                          (                              k                              )                                                                                ⁢                                                      cos                            ⁡                                                          (                              wt                              )                                                                                                                          ]                                                                                                                                              =                                                                    [                                                                  g                        ⁢                                                                                                  ⁢                        1                                            +                                              g                        ⁢                                                                                                  ⁢                                                  2                          ·                                                      cos                            ⁡                                                          (                              k                              )                                                                                                                                            ]                                    ⁢                                      sin                    ⁡                                          (                      wt                      )                                                                      -                                  g                  ⁢                                                                          ⁢                                      2                    ·                                          sin                      ⁡                                              (                        k                        )                                                                              ⁢                                      cos                    ⁡                                          (                      wt                      )                                                                                                                              equation        ⁢                                  ⁢                  (          1          )                    
Since the crossing point of AD(t) is defined as AD(t)=0, the corresponding value of wt is given bywt=arctan [g2·sin(k)/(g1+g2·cos(k))]  equation(2)
In other words, AD and thus ICK are waveforms with a phase shift from CK1 of a value expressed by equation(2).
It is noted that the value in equation(2) is a non-linear function of each of g1, g2 and k.
If CK1 and CK2 are triangular waves or square waves, the interpolated clock is a summation of all the sinusoidal harmonics of the g1·CK1 and g2·CK2.
Mathematically,AD(t)=g1·Σ(sinusoidal harmonics of CK1)+g2·Σ(sinusoidal harmonics of CK2)  equation(3)which is also a function of g1, g2 and the phase difference between CK1 and CK2. As a result, the phases of AD and ICK vary when any of the values of g1, g2, or k changes.
In the conventional phase interpolator, an interpolated signal is generated by analog elements which have inherent operational delay and this delay is directly reflected in the phase delay of the interpolated signal. Therefore, in order to secure phase matching between reference signals and the interpolated signal, the phase delays of the reference signals and the interpolated signal have to be controlled. The control of the phase delays of the reference signals and the interpolated signal requires additional circuits. Therefore, a clock data recovery system or the like using the phase interpolator becomes bigger and more complex while instability of phase relations between the reference signals and the interpolated signal remains.